Node Multiplier

The PomeLabs Node Multiplier Module (PML-NM-01) turns one Backend MCU into a four-node communication hub. Each port gets its own independent UART channel and its own dedicated ESD protection IC — so you can run four simultaneous serial conversations without any shared risk, any external components, or any compromise on signal integrity.

Revision: v1.0 | Part Number: PML-NM-01 | Series: PomeLabs Core Kit

Pinout

Node Multiplier Pinout

Schematic

Node Multiplier Schematic

Digital Twin

In the PomeLabs App, the PML-NM-01 is mirrored as a digital twin in both the Playground and inside any Connect Activity. Each of the four UART ports appears as an independent channel — send data from the App through any port and monitor what comes back in real time over the Connect bus.

Controls — parameters you can set from the App

UART TX — Port 1 · pin TX_1-L · serial data source

Drives USART1 transmit line through D1 ESD protection to the Port 1 node connector.

UART TX — Port 2 · pin TX_2-L · serial data source

Drives USART2 transmit line through D2 ESD protection to the Port 2 node connector.

UART TX — Port 3 · pin TX_3-L · serial data source

Drives USART3 transmit line through D3 ESD protection to the Port 3 Pogo connector (FE block).

UART TX — Port 4 · pin TX_4-L · serial data source

Drives USART4 transmit line through D4 ESD protection to the Port 4 Pogo connector (FE block).

Monitors — values streamed back from the module

UART RX — Ports 1–4 · pins RX_1-L … RX_4-L · serial data traces

Live inbound data from each downstream node, passed through the corresponding ESD protection device back to the Backend MCU.

Datasheet

1. Overview

The PML-NM-01 enables a single Backend MCU to communicate with up to four independent downstream nodes simultaneously through ESD-protected serial links, using four independent USART channels (USART1–USART4).

Each of the four ports is independently protected by a dedicated USBLC6-2P6 rail-to-rail ESD protection device (D1–D4), ensuring IEC 61000-4-2 Level 4 compliance on every TX/RX line. Ports 3 and 4 connect to field-side expansion nodes via 10-pin Magnetic Female Pogo connectors (J1NM, J2NM) inside a dedicated FE Function sub-block. Ports 1 and 2 connect to the upper pin-header connectors (P1, P2) on the module edge.

The architecture is deliberately symmetric — every port is treated identically in terms of protection topology and pull-up biasing, so any port can be assigned to any node without electrical asymmetry.

2. BOM Components

Ref.	Type	Value / Part	Role on this module
D1	ESD protection IC	USBLC6-2P6 (ST)	Primary ESD protection for Port 1 (Upper-Left). Rail-to-rail topology protects two data lines plus VBUS. IEC 61000-4-2 Level 4. $3.5\,\mathrm{pF}$ max I/O-to-GND. SOT-666 ( $1.6 \times 1.6\,\mathrm{mm}$ ).
D2	ESD protection IC	USBLC6-2P6 (ST)	Primary ESD protection for Port 2 (Upper-Right). Identical to D1.
D3	ESD protection IC	USBLC6-2P6 (ST)	Primary ESD protection for Port 3 (FE — Lower-Left). Protects the Pogo connector (J1NM) interface.
D4	ESD protection IC	USBLC6-2P6 (ST)	Primary ESD protection for Port 4 (FE — Lower-Right). Protects the Pogo connector (J2NM) interface.
J1NM, J2NM	Connector	10-Pin Magnetic Female Pogo	Node-side interface connectors for Ports 3 and 4 (FE Function block). Carry +5V, GND, S+/S−, and TX/RX signals between modules with self-aligning magnetic mating.
P1, P2	Connector	Pin headers	Edge-side interface connectors for Ports 1 and 2. Expose +5V, GND, S+/S−, RX/TX, TX/RX.
R1–R4	Resistor	$4.7\,\mathrm{k\Omega}$	Pull-up resistors on the post-protection TX/RX lines, biased to 3V3. Hold the lines in a defined HIGH state when no node is connected.

3. Electrical Specifications

All values at $T_{amb}$ = $25\,\mathrm{{}^\circ C}$ unless otherwise noted. ESD protection specifications from ST DS4260 Rev. 7 (USBLC6-2, December 2021). Pogo connector specifications are typical for industry-standard 10-pin magnetic spring-loaded connectors; consult the connector manufacturer's datasheet for the exact values used in production.

3.1 USBLC6-2P6

The USBLC6-2P6 is a monolithic 2-line + VBUS ESD protection device built on a rail-to-rail topology. Each I/O pin clamps to VBUS for positive surges (via a steering diode then a transil to GND) and to GND for negative surges (via a steering diode), suppressing IEC 61000-4-2 strikes without compromising signal integrity.

3.1.1 Absolute Maximum Ratings

Exceeding these values may permanently damage the device. Stress ratings only.

Parameter	Value	Unit
Peak pulse voltage ( $V_{PP}$ ) — IEC 61000-4-2 Level 4, air discharge	$15$	kV
Peak pulse voltage ( $V_{PP}$ ) — IEC 61000-4-2 Level 4, contact discharge	$15$	kV
Peak pulse voltage ( $V_{PP}$ ) — MIL-STD-883G method 3015-7	$25$	kV
Operating junction temperature ( $T_j$ )	$-40$ to $+150$	°C
Storage temperature ( $T_{stg}$ )	$-55$ to $+150$	°C
Maximum lead temperature for soldering ( $10\,\mathrm{s}$ at $5\,\mathrm{mm}$ )	$260$	°C

3.1.2 Electrical Characteristics

Parameter	Min	Typ	Max	Condition
Leakage current ( $I_{RM}$ )	—	$10\,\mathrm{nA}$	$150\,\mathrm{nA}$	$V_{RM}$ = $5.25\,\mathrm{V}$
Breakdown voltage ( $V_{BR}$ ), VBUS to GND	$6\,\mathrm{V}$	—	—	$I_R$ = $1\,\mathrm{mA}$
Forward voltage ( $V_F$ )	—	—	$1.1\,\mathrm{V}$	$I_F$ = $10\,\mathrm{mA}$
Clamping voltage ( $V_{CL}$ ), any I/O to GND	—	—	$12\,\mathrm{V}$	$I_{PP}$ = $1\,\mathrm{A}$ , $8/20\,\mathrm{\mu s}$
Clamping voltage ( $V_{CL}$ ), any I/O to GND	—	—	$17\,\mathrm{V}$	$I_{PP}$ = $5\,\mathrm{A}$ , $8/20\,\mathrm{\mu s}$
Capacitance I/O to GND ( $C_{i/o\text{-}GND}$ )	—	$2.5\,\mathrm{pF}$	$3.5\,\mathrm{pF}$	$V_R$ = $1.65\,\mathrm{V}$
Capacitance I/O to I/O ( $C_{i/o\text{-}i/o}$ )	—	$1.2\,\mathrm{pF}$	$1.7\,\mathrm{pF}$	$V_R$ = $1.65\,\mathrm{V}$
Capacitance matching tolerance ( $\Delta C_{i/o\text{-}GND}$ )	—	$0.015\,\mathrm{pF}$	—	I/O to GND

3.2 J1NM, J2NM — 10-Pin Magnetic Female Pogo Connector

Industry-typical specifications for 10-pin magnetic pogo connectors. Confirm against the connector vendor's datasheet for the production part.

Parameter	Typical Value	Notes
Number of contacts	$10$	Female receptacle, spring-pin mating
Contact resistance	$\leq 50\,\mathrm{m\Omega}$	Per pin, after mating cycles
Rated current per pin	$1$ – $3\,\mathrm{A}$	Depends on pin construction; verify against vendor datasheet
Insulation resistance	$\geq 100\,\mathrm{M\Omega}$	At $100\,\mathrm{V}$ DC
Mating cycles	$\geq 10\,000$	Typical durability rating
Operating temperature	$-40$ to $+85\,\mathrm{{}^\circ C}$	Industry-standard range
Spring force (per pin)	$30$ – $60\,\mathrm{gf}$	Typical range at working stroke
Mating alignment	Magnetic, self-aligning	Reverses orientation safely (verify magnet polarity)

4. Pin Descriptions

All signal pins are referenced to GND.

Pin / Net Name	Direction	Description
TX_1-L … TX_4-L	Input	UART transmit inputs from Backend MCU (USART1–USART4 TX). Each line carries outbound serial data for the corresponding node port.
RX_1-L … RX_4-L	Output	UART receive outputs back to Backend MCU (USART1–USART4 RX). Each line carries inbound serial data from the corresponding node port.
TX_*-P	Output	ESD-protected transmit lines to node-side connectors (post-USBLC6-2P6). For Ports 1–2 these go to P1/P2; for Ports 3–4 they go to J1NM/J2NM.
RX_*-P	Input	ESD-protected receive lines from node-side connectors (post-USBLC6-2P6). For Ports 1–2 these come from P1/P2; for Ports 3–4 from J1NM/J2NM.
5V-Bus	Power In	$5\,\mathrm{V}$ VBUS supply rail. Powers the VBUS pin of D1–D4 (required for clamping topology) and the +5V pin of all four port connectors.
3V3	Power In	$3.3\,\mathrm{V}$ logic rail used by the pull-up resistors R1–R4 ( $4.7\,\mathrm{k\Omega}$ ) on the post-protection TX/RX lines.
GND	Ground	Common ground. Shared across the Backend MCU, all four USBLC6-2P6 devices, and all connectors.
R1–R4 ( $4.7\,\mathrm{k\Omega}$ )	Passive	Pull-up resistors on the post-protection TX/RX lines to 3V3. Keep the lines at a defined HIGH idle state when no node is connected; also help suppress mid-rail noise.

5. Connection Guide & Common Errors

Correct power-up sequence:

Connect GND first, ensuring it is shared across the Backend MCU, the Node Multiplier, and any downstream node modules on the common bus.
Connect 5V-Bus to a regulated $5\,\mathrm{V}$ source. This rail powers the VBUS pin of all four USBLC6-2P6 devices — the rail must be present before the rail-to-rail ESD topology can clamp positive surges correctly.
Connect the 3V3 rail. The pull-up resistors R1–R4 use this rail to hold the idle UART lines HIGH.
Connect downstream nodes only after the supply rails are stable. Magnetic Pogo connectors (J1NM, J2NM) self-align — verify the magnet polarity is correct before forcing a mate.
Verify TX from the Backend MCU connects to RX on the downstream node and vice-versa (cross-wired UART). The labelling on the P1/P2 headers and Pogo pinouts assumes this convention.

Note on the ESD protection topology: the USBLC6-2P6 requires VBUS at $+5\,\mathrm{V}$ to clamp positive surges (it steers the surge through a diode to VBUS and then through an internal transil to GND). With 5V-Bus floating or absent, positive ESD strikes have no clean clamp path and the device may not protect downstream silicon. Always power 5V-Bus before any cable can be connected to a port.

Common wiring errors and consequences:

Mistake	Symptom	Correction
VBUS pin of any USBLC6-2P6 not connected to 5V-Bus	ESD clamp rail not established; positive ESD strikes are not clamped — downstream MCU UART pins exposed to surge	Always connect the VBUS pin of every USBLC6-2P6 to the 5V-Bus rail. Add a local $100\,\mathrm{nF}$ decoupling capacitor close to the VBUS pin if not already present on the board.
GND not shared across MCU, Node Multiplier, and downstream nodes	Ground offset corrupts UART signal levels (framing errors, wrong logic levels); ESD return path missing — clamp ineffective	Ensure a single common GND bus shared between the Backend MCU, all four USBLC6-2P6 devices, and every connected node module. Avoid star-ground topologies with thin return traces.
TX and RX swapped at a connector	No communication; UART framing errors or silence	Verify TX from the MCU side maps to RX of the downstream node (and vice-versa) at each connector. Pogo connectors are not symmetrical despite the magnetic mating — confirm pinout.
Pull-ups R1–R4 not biased to 3V3 (rail unconnected)	Idle UART lines float; spurious break or framing detection on disconnected ports	Connect the 3V3 rail. The pull-ups hold the lines at a clean HIGH between transmissions and when a port has no node attached.
Long traces between USBLC6-2P6 and the connector	Parasitic inductance ( $L \cdot dI/dt$ ) adds significant overshoot to $V_{CL}$ — TI's example shows ${\approx}6\,\mathrm{nH}$ per $10\,\mathrm{mm}$ of trace can add ${\approx}140\,\mathrm{V}$ to the clamp voltage at $dI/dt$ = $24\,\mathrm{A/ns}$	Place each USBLC6-2P6 as physically close to its connector as the layout permits. Keep VBUS, I/O, and GND traces short and direct.
ESD line length asymmetry between paired data lines	Skew / crosstalk degradation on differential signalling	The $0.015\,\mathrm{pF}$ I/O-to-GND capacitance matching of the USBLC6-2P6 only delivers its full benefit if PCB traces are length-matched too. Route paired lines together with equal length.
5V-Bus exceeds $6\,\mathrm{V}$	VBUS pin breakdown ( $V_{BR}$ = $6\,\mathrm{V}$ min) — clamp may begin to conduct under normal operation; long-term reliability degraded	Keep the 5V-Bus rail at $+5\,\mathrm{V}$ nominal, $\leq 5.5\,\mathrm{V}$ worst case. Do not share this rail with higher-voltage supplies.
Pogo connector mated dirty / dusty	Increased contact resistance — UART signal degradation, intermittent comms	Wipe the female receptacle and the mating pads periodically with isopropyl alcohol. Magnetic pogo connectors are typically rated for $\geq 10\,000$ mating cycles when kept clean.

Node Multiplier

Pinout

Schematic

Digital Twin

Controls — parameters you can set from the App

Monitors — values streamed back from the module

Datasheet

1. Overview

2. BOM Components

3. Electrical Specifications

3.1 USBLC6-2P6

3.1.1 Absolute Maximum Ratings

3.1.2 Electrical Characteristics

3.2 J1NM, J2NM — 10-Pin Magnetic Female Pogo Connector

4. Pin Descriptions

5. Connection Guide & Common Errors

Hands-on Labs

Node Multiplier Onboarding

Multi-Node Communication

ESD Protection Verification

Pogo Connector Interface

Use Cases

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